Low Power Schottky TTL logic levels

Operating conditions: VCC 4.75 V min. to 5.25 V max.
74LSXX chips

For standard TTL click here

PARAMETER

CONDITIONS

MIN

MAX

UNITS

Logic 1
input voltage		VCC = min2.0--V
Logic 0,
input voltage		VCC = min--0.8V
Logic 1,
output voltage		VCC = min - - Iout= - 400 mA2.7--V
Logic 0,
output voltage		VCC = min - - Iout= 8 mA--0.5V
Logic 1,
input current		VCC = min - - Vin = 2.7 V--- 20mA
Logic 1,
input current		VCC = min - - Vin = 7.0 V--0.1mA
Logic 0,
input current		VCC = min - - Vin = 0.4 V--- 0.4mA

logic

What does it all mean?
VOH Min = Output voltage high minimum with up to 400 mA load
A good chip is guaranteed to output a minimum of 2.7 V logic high up to 400 mA

VOL Max = Output voltage low maximum with up to 8 mA load
A good chip is guaranteed to output a maximum of 0.5 volts up to 8 mA

VIH Min = Input voltage high minimum 2.0 V
A good chip will recognize 2.0 V or greater as a logic high and draw no more than 20mA input current.

VIL Min = Input voltage low maximum 0.8 V
A good chip will recognize 0.8 V or less as a logic low and draw no more than 0.4 mA input current.


Fan out

 For a logic high, a good LS family chip will source 400 mA and maintain a minimum of 2.4 V
For a logic high, the input will draw no more than 40 mA

For a logic low, a good LS family chip will sink 8 mA and hold the voltage at 0.5 V maximum.
For a logic low, the input will draw no more than 0.4 mA

The fan out for LS family chips is usually given as 20. Fan out only applies when driving inputs of the same family.
An LS chip at 8 mA low out would only drive 5 stantard TTL inputs at 1.6 mA each.

Noise Margin

 Notice the 300 mV difference between the specified output voltage of an LS TTL chip and the input voltage required to recognize a logic low level. This 300 mV difference provides a margin such that noise added to the signal does not cause errors. An output voltage with up to 300 mV peak of noise added will still provide a valid logic level to the input of the next stage. The noise margin for a logic high signal is greater, but you always need to use the worst case which in the case of an LS family chip is 300 mV.